1. Field of the Invention
The present invention relates to a semiconductor memory including an error correction function by use of an error correction code (ECC) and, more particularly, to a semiconductor memory including no resetting functions that are used, for example, in a mass-storage SRAM.
2. Description of the Related Art
With an improvement in fine patterning and storage capacity of a semiconductor memory, manufacturing technologies have been becoming more sophisticated and difficult to implement, thus making it difficult to manufacture at a high yield such a memory product that all memory cells in the memory operate properly. Further, improved fine patterning has reduced a capacitance to be held in each bit cell, thus causing a phenomenon of random destruction of a one-bit error (which is referred to as a soft error) owing to cosmic radiation or alpha radiation to occur frequently to such an extent that it cannot be ignored. This soft error phenomenon cannot be repaired by redundancy technologies and so has been becoming a big problem. As one solution for this problem, a memory has a correction function inside.
FIG. 6 shows part of a DRAM having a conventional error correction function.
This DRAM comprises: an input/output (I/O) circuit 10 for sending input data/output data to and receiving them from an outside of the DRAM; a data memory (main memory) 11 which has a plurality of memory regions to store n-bit data in a specified address; a code memory 12 which has the same address area as the data memory 11 and which stores an m-bit (m<n) code (ECC) which enables correcting each piece of data stored in each of the memory regions of the data memory 11; and an ECC control circuit 13 provided to control these components.
FIG. 7 shows a conventional example of the ECC control circuit 13 of FIG. 6.
This ECC control circuit comprises a read data register 23, an ECC code register 24, an ECC code generation circuit 25, a syndrome generation circuit 26, an ECC decoding circuit (syndrome decoder) 27, and a correction data register 28, thus having the following basic functions.
(1) In data reading before ordinary data writing, n-bit data read from the data memory 11 is stored in read data register 23, while simultaneously an m-bit ECC code read from the code memory 12 is stored in the ECC code register 24. Then, for the data read from the data memory 11, an m-bit ECC code is generated by the ECC code generation circuit 25. The generated ECC code is compared to the ECC code read from the code memory 12 by the syndrome generation circuit 26, thereby generating an error correction code, which is referred to as a syndrome. If, in this case, the two ECC codes agree, the syndrome code is “0”, and if a specific one bit in the read data or the ECC code has been inverted, the syndrome code takes on a value other than “0”.
If the syndrome code is “0”, the ECC decoding circuit (syndrome decoder) 27 decides that the inputted data has been saved properly. If the syndrome code is a specific value other than “0”, on the other hand, it can be decided which bit is not correct because the syndrome code is in one-to-one correspondence with an inversed bit and so corrects it.
Subsequently, in data writing, for input data to be written in the data memory 11 from the I/O circuit 10, an ECC code is generated by the ECC code generation circuit 25. Then, this ECC code is stored in the code memory 12.
(2) In ordinary data reading, the same operation as in the above described data reading before ordinary data writing is performed. In this case, data stored in the read data register 23 passes through the correction data resister 28 as it is or is corrected one bit in the correction data resister 28, to provide output data.
As described above, a DRAM including the ECC function is capable of correcting a data error of up to one bit for each data in each address and outputting it, thus enabling suppressing a data error rate due to a soft error that cannot be repaired. Furthermore, it also has an effect of repairing bit failures that may occur in a process, if the failure rates are reasonably low.
It is to be noted that, for example, generally an SRAM does not include the resetting function for a reason in specifications. In a case where the ECC control circuit 13 such as shown in FIG. 6 is incorporated in such a memory, immediately after power application, a relationship between data in the read data memory 11 and ECC codes in the code memory 12 are in a random condition (in a condition where there is no correlation about the ECC code), so that the ECC function does not operate properly.
Further, in a case where the ECC control circuit having an ECC function dedicated as a one-bit correction function generally used often is incorporated in the SRAM, immediately after power application, it cannot be accommodated if a data error of at least two bits has occurred in the data in the data memory 11 and the ECC code in the code memory 12. In such a case, when data reading is performed to the data memory 11 and the code memory 12 for the first time after power application, an originally error-free one bit in the data read from the data memory 11 is corrected mistakenly at a high probability.
That is, if an ECC code generated for data read from the data memory 11 and an ECC code read from the code memory 12 are compared to each other to thereby create a syndrome code, the syndrome code takes on a specific value other than “0”, so that one bit of the originally correct data may possibly be corrected mistakenly, which is a problem.
The following will consider a case where a bit width n of the data memory 11 is set larger than a bit width of input/output data of the I/O circuit 10 or such a function (mask function) is provided as to write only some bits of input data in the data memory 11. In this case, in order to create an ECC code in first data writing after power application, data needs to be read from the data memory beforehand and referred to, so that it is difficult to avoid the above mistaken correction problem, resulting in writing back an incorrect ECC code.
Furthermore, if the ECC control circuit 13 is applied to take measures not only against a soft error but also against a fixed bit failure, this problem is fatal. That is, if a fixed single-bit failure is present in a memory region having an address specified when data is written first after power application, when data is read next, a total of two bits of this failed bit and a mistakenly corrected bit are decided to be failed, so that this read data is read as incorrect data at a high probability.
Jpn. Pat. Appln. KOKAI Publication No. 2000-242515 discloses a method by which, to verify a function of the ECC control circuit, a bit position where a one-bit error has been generated and a bit position where a one-bit error has been detected by the ECC control circuit from outputs of two selectors are compared to each other, so that a data value before the occurrence of the one-bit error and a data value after correction of the one-bit error by the ECC control circuit are compared to each other.